MIT/Lincoln Labs CCID20 W91C2 CCD Test Results

This is a phase 2 MIT/Lincoln Labs 2Kx4K CCD employing the new backside boron implant and laser anneal process that improves QE spatial uniformity. This is a 300 ohm-cm epi CCD.

A summary report is available. Noteworthy points about this CCD include:

In MIT/Lincoln tests this device was rated A. We concur with that rating.
The new backside processing gives this device better QE uniformity than the phase 1 CCDs.
Other characteristics (QE, read noise, full well, etc.) as shown in the summary report are typical.

Original postscript files are available from our anonymous ftp server and these provide better resolution and clarity than is usually possible on a web page. Here are a few figures to illustrate device highlights:

Residual image: These images illustrate the effect of parallel clock voltages on the presence of residual charge.
Serial CTE: CTE measurements are generally very good, with perhaps one slight imperfection.
Surface flatness: This CCD is pretty flat.

To obtain these images the CCD was first exposed to the test pattern, with about 700,000 electrons generated in the brightest areas. Full well is roughly 100,000 electrons. The CCD was read out. Then a 1000s exposure was taken (which includes 8 initial CCD erase cycles). Both of these images have essentially the same background level. But they were displayed slightly differently, so that one image appears to have a darker background level. The first image (with the background appearing dark) was obtained using parallel clocks switching between +2v and -6v. Under these conditions the residual image is rather severe. The second image was obtained using parallel clocks switching between +2 and -8v. Here the residual image is very much reduced.

The reduction in residual image is to be expected using -8v because the Si/SiO₂ interface is driven into inversion. One feature of the second image we don't yet understand is the behavior of the center part of the image. Because of the small feature size, the bars in the test pattern were actually less bright than the larger bars around the edge. Yet in the second image that area appears brightest in the residual image.

These tests suggest that one might want to use +2 and -8v for the parallel clocks, or perhaps even a little more negative voltage to try to eliminate the residual image. However, as the following table shows, spurious charge generation may increase dramatically when the Si/SiO₂ interface is inverted. This problem may be controllable with very slow rise times on the parallel clocks (the negative-to-positive transition generates the spurious charge) or with multi-level clocks. The problem is significant and must be examined carefully by anyone wishing to maintain the low read-noise of the CCID20.

Residual image observed in W91C2 for three parallel clock voltages

row #    2,-6    2,-8    2,-10
200     0.19    6.2     14.6
600     0.36    7.0     18.2
1000    0.15    7.7     22.9
1400    0.0     7.9     26.9
1800    0.0     8.7     31.8
2200    0.69    9.7     41.6
2600    0.39    10.0    46.8
3000    0.74    10.9    52.1
3400    0.04    11.3    57.0

The Lincoln CCID20 design produces excellent charge transfer efficiency. This device appears to have a slight trap in the serial register near one end (indicated by the green arrow). The CTE listed in the report (0.999984) is shown by the line in the plot. Clearly this fit to the data is biased by the trap and the CTE is much better than this over most of the array. No attempt has been made to adjust serial clock voltages to reduce the effects of the charge trap.

This CCD has about 11 µm of curvature, peak-to-peak, at room temperature.

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